{"id":1907,"date":"2010-07-08T03:38:51","date_gmt":"2010-07-07T22:08:51","guid":{"rendered":"http:\/\/www.jeffrin.in\/?p=1907"},"modified":"2010-07-08T03:38:51","modified_gmt":"2010-07-07T22:08:51","slug":"16-bits-into-the-segment-registergs-02","status":"publish","type":"post","link":"https:\/\/www.trueangle.org\/index.php\/2010\/07\/08\/16-bits-into-the-segment-registergs-02\/","title":{"rendered":"16 bits into the segment register…(GS)"},"content":{"rendered":"

software | Windows | <\/h3>\n
\n \"\"<\/a>\n<\/pre>\n
\nThese instructions read a full pointer from memory and store it in the\nselected segment register:register pair. The full pointer loads 16 bits\n into the segment register SS, DS, ES, FS, or GS\n\n\nsource :\nhttp:\/\/pdos.csail.mit.edu\/6.828\/2008\/readings\/i386\/LGS.htm\n<\/pre>\n
 software |GNU\/Linux| <\/h3>\n
\n(gdb) info  registers\nrax            0xfffffffffffffdfc\t-516\nrbx            0x5dc\t1500\nrcx            0xffffffffffffffff\t-1\nrdx            0x5dc\t1500\nrsi            0x1\t1\nrdi            0x7fff599ac280\t140734696702592\nrbp            0x1f08af0\t0x1f08af0\nrsp            0x7fff599ac230\t0x7fff599ac230\nr8             0x0\t0\nr9             0xffffffff\t4294967295\nr10            0x8\t8\nr11            0x246\t582\nr12            0x7fff599ac280\t140734696702592\nr13            0x7fff599ac290\t140734696702608\nr14            0x0\t0\nr15            0x1\t1\nrip            0x7f0129e710c8\t0x7f0129e710c8 \neflags         0x246\t[ PF ZF IF ]\ncs             0x33\t51\nss             0x2b\t43\nds             0x0\t0\nes             0x0\t0\nfs             0x0\t0\ngs             0x0\t0\n(gdb)\n\nInstead of FS segment descriptor on x86 versions of the Windows NT\nfamily, GS segment descriptor is used to point to two operating system\ndefined structures: Thread Information Block (NT_TIB) in user mode\nand Processor Control Region (KPCR) in kernel mode. Thus, for example,\nin user mode GS:0 is the address of the first member of the Thread\n Information Block. Maintaining this convention made the x86-64 port\n easier, but required AMD to retain the function of the FS and GS\n segments in long mode \u2014 even though segmented addressing per se is\n not really used by any modern operating system.[38]\n\nsource :\nhttp:\/\/en.wikipedia.org\/wiki\/X86-64\n\n<\/pre>\n
 | Related Discussion |<\/h3>\n
\nleilei wrote:\nI am writting a program for target board which have a 486 cpu, 512K\nram(0x0 to 0x7ffff), 512k flash (0x80000 to 0xFFFFF).My program will\nbe burned into flash.\nMy program is to initialize the GDT, IDT, TSS, move them to memory.\nNow I can enter protected model and mov GDT, IDT correctly.But when I\nam about to mov TSS, some exception came out, and the CPU reset\nautomaticly. The code casue the problem is like this:\nmov cx, gdt_idx\nmov gs, cx\nwhen cpu run to the instuction 'mov gs, cx', CPU will reset.\ni can assure the value in cx is correctly.\n\ncan any one give me some tips about how can this be happend?\n\n\nThis seems to have nothing to do with TSS, yet.\nThe CPU is not happy with the selector attempted\nto load GS with.\n\nPlease check that the number in CX is a valid GDT\nselector within the table range.\n\nIt also seems that there is no handler available\nfor the exception generated by the segment loading.\n\n--\n\nTauno Voipio\ntauno voipio (at) iki fi\n\nsource :\nhttp:\/\/coding.derkeiler.com\/Archive\/General\/comp.arch.embedded\/2008-04\/msg01432.html\n\n<\/pre>\n
\n
| Variation |<\/h3>\nI think eax has a typical closer connection to 32 bit\nsoftware architecture of an operating system and rax\nis like for 64 bit OS.\n\nLink(s).\n\nhttp:\/\/lists.xensource.com\/archives\/html\/xen-devel\/2006-12\/msg00547.html\n\n<\/pre>\n","protected":false},"excerpt":{"rendered":"
software | Windows | These instructions read a full pointer from memory and store it in the selected segment register:register pair. The full pointer loads 16 bits into the segment register SS, DS, ES, FS, or GS source : http:\/\/pdos.csail.mit.edu\/6.828\/2008\/readings\/i386\/LGS.htm software |GNU\/Linux| (gdb) info registers rax 0xfffffffffffffdfc -516 rbx 0x5dc 1500 rcx 0xffffffffffffffff -1 rdx … <\/p>\n
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