{"id":1955,"date":"2010-07-09T21:42:37","date_gmt":"2010-07-09T16:12:37","guid":{"rendered":"http:\/\/www.jeffrin.in\/?p=1955"},"modified":"2010-07-09T21:42:37","modified_gmt":"2010-07-09T16:12:37","slug":"the-intel-ia32-processors-have-a-base-pointer","status":"publish","type":"post","link":"https:\/\/www.trueangle.org\/index.php\/2010\/07\/09\/the-intel-ia32-processors-have-a-base-pointer\/","title":{"rendered":"The Intel IA32 processors have a base pointer.."},"content":{"rendered":"
\n
 software | Windows | <\/h3>\n<\/pre>\n
\n\"\"<\/a>\n<\/pre>\n
\nThe Intel IA32 processors have a base pointer register called EBP . The\nEBP register is typically set to the value of the ESP register at the\n beginning of a procedure, and used to address the procedure arguments\n and locally allocated variables throughout the procedure. Thus, the\n arguments are located at positive offsets from the EBP register, while the\n variables are located at negative offsets from the EBP register.\n\nsource :\nhttp:\/\/d3s.mff.cuni.cz\/~ceres\/sch\/osy\/text\/ch03s02s02.php\n<\/pre>\n
\n
 software | GNU\/Linux | <\/h3>\n<\/pre>\n
\n(gdb) info registers\nrax            0xfffffffffffffdfc\t-516\nrbx            0x5dc\t1500\nrcx            0xffffffffffffffff\t-1\nrdx            0x5dc\t1500\nrsi            0x1\t1\nrdi            0x7ffffb2814d0\t140737407096016\nrbp            0x1f70160\t0x1f70160\nrsp            0x7ffffb281480\t0x7ffffb281480\nr8             0x0\t0\nr9             0xffffffff\t4294967295\nr10            0x8\t8\nr11            0x246\t582\nr12            0x7ffffb2814d0\t140737407096016\nr13            0x7ffffb2814e0\t140737407096032\nr14            0x0\t0\nr15            0x1\t1\nrip            0x7f668b3710c8\t0x7f668b3710c8 \neflags         0x246\t[ PF ZF IF ]\ncs             0x33\t51\nss             0x2b\t43\nds             0x0\t0\nes             0x0\t0\nfs             0x0\t0\ngs             0x0\t0\n(gdb)\n\n
  rbp            0x1f70160\t0x1f70160 <\/h4>\n<\/pre>\n
\nIn computer architecture, a processor register (or general purpose\n register) is a small amount of storage available on the CPU whose\n contents can be accessed more quickly than storage available\n elsewhere.\nsource :\nhttp:\/\/en.wikipedia.org\/wiki\/Processor_register\n\nThe AMD64 architecture has sixteen 64-bit general purpose registers\n (GPRs): RAX, RBX, RCX, RDX, RBP<\/b>, RSI, RDI, RSP, R8, R9, R10, R11, R12,\n R13, R14, and R15. Compared to the x86 architecture, the AMD64\n architecture has eight new GPRs.\n\nsource :\nhttp:\/\/developers.sun.com\/solaris\/articles\/x64_dbx.html\n<\/pre>\n
\n
 | Related Discussion | <\/h3>\n<\/pre>\n
\n Hi, Could somebody please explain what GCC is doing for this piece of code? What is it initializing? The original code is:\n\n#include \nint main()\n{\n\n}\nAnd it was translated to:\n\n    .file       \"test1.c\"\n    .def        ___main;        .scl    2;      .type   32;     .endef\n    .text\n.globl _main\n    .def        _main;  .scl    2;      .type   32;     .endef\n_main:\n    pushl       %ebp\n    movl        %esp, %ebp\n    subl        $8, %esp\n    andl        $-16, %esp\n    movl        $0, %eax\n    addl        $15, %eax\n    addl        $15, %eax\n    shrl        $4, %eax\n    sall        $4, %eax\n    movl        %eax, -4(%ebp)\n    movl        -4(%ebp), %eax\n    call        __alloca\n    call        ___main\n    leave\n    ret\n<\/pre>\n
\n
 | Variation | <\/h3>\n<\/pre>\n
\nRegisters E(SP), E(IP) and E(BP) are promoted to 64-bits and are re-named RSP, RIP, and RBP respectively.\n\nsource and link(s) :\nhttp:\/\/x86asm.net\/articles\/x86-64-tour-of-intel-manuals\/\n<\/pre>\n","protected":false},"excerpt":{"rendered":"
software | Windows | The Intel IA32 processors have a base pointer register called EBP . The EBP register is typically set to the value of the ESP register at the beginning of a procedure, and used to address the procedure arguments and locally allocated variables throughout the procedure. Thus, the arguments are located at … <\/p>\n
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