{"id":1975,"date":"2010-07-10T18:19:32","date_gmt":"2010-07-10T12:49:32","guid":{"rendered":"http:\/\/www.jeffrin.in\/?p=1974"},"modified":"2010-07-10T18:19:32","modified_gmt":"2010-07-10T12:49:32","slug":"1974","status":"publish","type":"post","link":"https:\/\/www.trueangle.org\/index.php\/2010\/07\/10\/1974\/","title":{"rendered":"eip in 32-bit mode,, and rip in 64-bit mode"},"content":{"rendered":"

software | Windows |<\/h3>\n
\n\"\"<\/a>\n<\/pre>\n
\nThe instruction pointer is called ip in 16-bit mode, eip in 32-bit mode,,\n and rip in 64-bit mode. The instruction pointer register points to the\n memory address which the processor will next attempt to execute; it\n cannot be directly accessed in 16-bit or 32-bit mode, but a sequence\n like the following can be written to put the address of next_line into\n eax:\n    call next_line\nnext_line:\n    pop eax\n\nsource :\nhttp:\/\/en.wikipedia.org\/wiki\/X86_assembly_language\n<\/pre>\n
 software | GNU\/Linux | <\/h3>\n
\n(gdb) info registers\nrax            0xfffffffffffffdfc\t-516\nrbx            0x5dc\t1500\nrcx            0xffffffffffffffff\t-1\nrdx            0x5dc\t1500\nrsi            0x1\t1\nrdi            0x7fff09cf5780\t140733357971328\nrbp            0x2051160\t0x2051160\nrsp            0x7fff09cf5730\t0x7fff09cf5730\nr8             0x0\t0\nr9             0xffffffff\t4294967295\nr10            0x8\t8\nr11            0x246\t582\nr12            0x7fff09cf5780\t140733357971328\nr13            0x7fff09cf5790\t140733357971344\nr14            0x0\t0\nr15            0x1\t1\nrip            0x7f2e947000c8\t0x7f2e947000c8 \neflags         0x246\t[ PF ZF IF ]\ncs             0x33\t51\nss             0x2b\t43\nds             0x0\t0\nes             0x0\t0\nfs             0x0\t0\ngs             0x0\t0\n(gdb)\n<\/pre>\n
\n
 rip            0x7f2e947000c8\t0x7f2e947000c8 <\/h4>\n<\/pre>\n
\nThe RIP register is the instruction pointer register. In 64-bit mode, the\n RIP register is extended to 64 bits to support 64-bit offsets. In 32-bit\n x86 architecture, the instruction pointer register is the EIP register.\n\nsource:\nhttp:\/\/developers.sun.com\/solaris\/articles\/x64_dbx.html\n<\/pre>\n
 | Related Discussion | <\/h3>\n
\nHi...I'm teaching myself some AMD 64 bit assembler programing and I'm\ncurious about RIP relative addressing. The docs that I've read state\n \"You are recommended to use RIP relative addressing whenever possible\n to reduce code size\" now my question is, is this the code size reduction\n they are talking about\n\n\nCode:\nexample code 1 RIP-relative addressing\n\n.section .data\n\tmydata: .long 0\n\n.section .bss\n\n.section .text\n\t.global _start\n_start:\n\t\t\tmovq\t$64, mydata(%rdi)\nCode:\nexample code 2\n.section .data\n\tmydata: .long 0\n\n.section .bss\n\n.section .text\n\t.global _start\n_start:\n\t\t\tmovq\t$64, mydata\nand the results\n\nCode:\nexample 1 RIP-relative addressing\ncode1:     file format elf64-x86-64\n\n\nDisassembly of section .text:\n\n00000000004000b0 :\n  4000b0:\t48 c7 87 bc 00 60 00 \tmovq   $0x40,0x6000bc(%rdi)\n  4000b7:\t40 00 00 00\nCode:\nexample 2\ncode2:     file format elf64-x86-64\n\n\nDisassembly of section .text:\n\n00000000004000b0 :\n  4000b0:\t48 c7 04 25 bc 00 60 \tmovq   $0x40,0x6000bc\n  4000b7:\t00 40 00 00 00\nare we talking about a one byte reduction in code size every time I use RIP relative addressing?\n\nsource :\nhttp:\/\/www.linuxforums.org\/forum\/linux-programming-scripting\/131795-amd-64-bit-rip-relative-addressing.html\n<\/pre>\n
 | Variation | <\/h3>\n
\nHow RIP\/EIP relative addressing works in 32-bit mode\n\nIn 32-bit programs you can't do this :\n\nmov al, [eip]\n\nBut you will have to do something like this instead :\ncall $ + 5\npop ebx\nadd ebx, 1 + 1 + 1 + 1 ; POP + ADD + ModRM + imm8\nmov al, [ebx] ; EBX is now pointing to this instruction!\n\n\n\nHow RIP\/EIP relative addressing works in 64-bit mode\n\nIn 64-bit programs you are allowed to write this :\nmov al, [rip]\n\nsource :\nhttp:\/\/www.codegurus.be\/codegurus\/Programming\/riprelativeaddressing_en.htm\n\n\n<\/pre>\n","protected":false},"excerpt":{"rendered":"
software | Windows | The instruction pointer is called ip in 16-bit mode, eip in 32-bit mode,, and rip in 64-bit mode. The instruction pointer register points to the memory address which the processor will next attempt to execute; it cannot be directly accessed in 16-bit or 32-bit mode, but a sequence like the following … <\/p>\n
Continue reading “eip in 32-bit mode,, and rip in 64-bit mode”<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[22],"tags":[640,701,811,950,1035,1277,1680],"_links":{"self":[{"href":"https:\/\/www.trueangle.org\/index.php\/wp-json\/wp\/v2\/posts\/1975"}],"collection":[{"href":"https:\/\/www.trueangle.org\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.trueangle.org\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.trueangle.org\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.trueangle.org\/index.php\/wp-json\/wp\/v2\/comments?post=1975"}],"version-history":[{"count":0,"href":"https:\/\/www.trueangle.org\/index.php\/wp-json\/wp\/v2\/posts\/1975\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.trueangle.org\/index.php\/wp-json\/wp\/v2\/media?parent=1975"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.trueangle.org\/index.php\/wp-json\/wp\/v2\/categories?post=1975"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.trueangle.org\/index.php\/wp-json\/wp\/v2\/tags?post=1975"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}