Kernel Panic….

Call Trace: {panic+483} {_spin_unlock_ irq+12} {__down_read+60} {_spin_lock_irqsave+ 9} {__up_read+25} {blocking_notifier_cal l_chain+70} {do_exit+141} {kernel_math_error+0} <ffffffff80270dfc}{do_invalid_op+173} {:aacraid:aac_intr _normal+463} <fffffff80269ece}{spin_lock_irqsave+9} {printk+82} {error_exit+0} {vgacon_cursor+0} {:aacraid:aac_intr_normal+473} {:aacr aid:aac_intr_normal+473} {:aacraid:aac_rx_intr+55} {handle_IRQ _event+41} {__do_IRQ+154} {do_IRQ+60} {ret_from_intr+0} (3) astrax:/home/pgperez> (3) astrax:/home/pgperez> cat error {:aacraid:aac_rx_intr+55} {handle_IRQ_event+41} {__do_IRQ+154} {do_IRQ+60} {ret_from_intr+0} link : https://bugzilla.redhat.com/show_bug.cgi?format=multiple&id=205778

eip in 32-bit mode and rip in 64-bit mode

ABOUT Processor Register In computer architecture, a processor register is a quickly accessible location available to a computer’s central processing unit (CPU). Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. Registers are typically addressed by mechanisms other than main memory, …

The Intel IA32 processors have a base pointer..

software | Windows | The Intel IA32 processors have a base pointer register called EBP . The EBP register is typically set to the value of the ESP register at the beginning of a procedure, and used to address the procedure arguments and locally allocated variables throughout the procedure. Thus, the arguments are located at …

16 bits into the segment register…(GS)

software | Windows | These instructions read a full pointer from memory and store it in the selected segment register:register pair. The full pointer loads 16 bits into the segment register SS, DS, ES, FS, or GS source : http://pdos.csail.mit.edu/6.828/2008/readings/i386/LGS.htm software |GNU/Linux| (gdb) info registers rax 0xfffffffffffffdfc -516 rbx 0x5dc 1500 rcx 0xffffffffffffffff -1 rdx …