BEAUTY AND PLAY
H:>pause
Press any key to continue . . .
H:>pause /?
Suspends processing of a batch program and displays the message
Press any key to continue . . .
H:>pause
Press any key to continue . . .
Pause Suspends processing of a batch program and displays a message prompting the user to press any key to continue. source : http://www.microsoft.com/resources/documentation/windows/xp/all/proddocs/en-us/ntcmds.mspx?mfr=true
H:\>pause
Press any key to continue . . .
H:\>pause /?
Suspends processing of a batch program and displays the message
Press any key to continue . . .
H:\>pause
Press any key to continue . . .
Pause Suspends processing of a batch program and displays a message prompting the user to press any key to continue. source : http://www.microsoft.com/resources/documentation/windows/xp/all/proddocs/en-us/ntcmds.mspx?mfr=true
In computing, a code segment, also known as a text segment or simply as text, is a phrase used to refer to a portion of memory or of an object file that contains executable instructions. source : http://en.wikipedia.org/wiki/Code_segment Note that code may always modify all segment registers except CS (the code segment). This is because the current privilege level (CPL) of the processor is stored in the lower 2 bits of the CS register. The only way to raise the processor privilege level (and reload CS) is through the lcall (far call) and int (interrupt) instructions. Similarly, the only way to lower the privilege level (and reload CS) is through lret (far return) and iret (interrupt return). source : http://en.wikipedia.org/wiki/X86_memory_segmentation
(gdb) info registers rax 0xfffffffffffffdfc -516 rbx 0x5dc 1500 rcx 0xffffffffffffffff -1 rdx 0x5dc 1500 rsi 0x1 1 rdi 0x7fff6f396d50 140735059422544 rbp 0xb4a160 0xb4a160 rsp 0x7fff6f396d00 0x7fff6f396d00 r8 0x0 0 r9 0xffffffff 4294967295 r10 0x8 8 r11 0x246 582 r12 0x7fff6f396d50 140735059422544 r13 0x7fff6f396d60 140735059422560 r14 0x0 0 r15 0x1 1 rip 0x7fc4561ec0c8 0x7fc4561ec0c8 eflags 0x246 [ PF ZF IF ] cs 0x33 51 ss 0x2b 43 ds 0x0 0 es 0x0 0 fs 0x0 0 gs 0x0 0 (gdb)cs 0x33 51
Register operands are always prefixes with `%'. The 80386 registers consist of the 6 section registers `%cs' (code section), `%ds' (data section), `%ss' (stack section), `%es', `%fs', and `%gs'. source : http://www.cs.utah.edu/dept/old/texinfo/as/as.html#SEC152
CS Register Setting by VnutZ :: NR10 :: Show The article correctly mentions the importance of setting up segment registers, yet like most neglects to set up CS (which is 0×0000). This is one nasty latent bug that shows itself as soon as you try doing indirect jumps. So if you want to use something like threaded code in your first stage bootloader set CS by "jmp 0×07c0:foo" first. You’re right – it would have been "good practice" to set the CS register. However, the CS register is already correctly set by the BIOS. If it were not set … a computer would never boot up! CS (code segment) and IP (instruction pointer) are both set to point directly at 0000:7C00 which is where the BIOS loads the bootsector into. source: http://www.omninerd.com/comments/10807
The way to execute user processes in kernel mode in AMD64 is almost the same as it is in IA-32. To execute user processes in kernel mode, the only thing KML does is launch user processes with the CS segment register, which points to the kernel code segment instead of user code segment. In AMD64 CPUs, the privilege level of running programs is determined by the privilege level of their code segment. This is almost the same as in IA-32 CPUs; the only difference is the segmentation memory system is degenerated in AMD64. Although segment registers still are used in 64 -bit mode of AMD64, the only segment that the segment registers can use is the 16 EB flat segment. Thus, the role of the segment descriptors is simply to specify privilege levels. Therefore, only four segments—kernel code segment, kernel data segment, user code segment—exist in 64-bit mode. source and link(s) : http://www.linuxjournal.com/article/8023?page=0,1 http://www.thefreedictionary.com/degenerated
ABOUT Processor Register
In computer architecture, a processor register is a quickly accessible location available to a computer's central processing unit (CPU). Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. Registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.
[bash light=”true”]
(gdb) info registers
rax 0xfffffffffffffdfc -516
rbx 0x5dc 1500
rcx 0xffffffffffffffff -1
rdx 0x5dc 1500
rsi 0x1 1
rdi 0x7fff09cf5780 140733357971328
rbp 0x2051160 0x2051160
rsp 0x7fff09cf5730 0x7fff09cf5730
r8 0x0 0
r9 0xffffffff 4294967295
r10 0x8 8
r11 0x246 582
r12 0x7fff09cf5780 140733357971328
r13 0x7fff09cf5790 140733357971344
r14 0x0 0
r15 0x1 1
rip 0x7f2e947000c8 0x7f2e947000c8
eflags 0x246 [ PF ZF IF ]
cs 0x33 51
ss 0x2b 43
ds 0x0 0
es 0x0 0
fs 0x0 0
gs 0x0 0
(gdb)
[/bash]
The RIP register is the instruction pointer register. In 64 -bit mode, the RIP register is extended to 64 bits to support 64-bit offsets. In 32-bit x86 architecture, the instruction pointer register is the EIP register.source:
Related STUFF
[text]
Code:
example code 1 RIP-relative addressing
.section .data
mydata: .long 0
.section .bss
.section .text
.global _start
_start:
movq $64, mydata(%rdi)
Code:
example code 2
.section .data
mydata: .long 0
.section .bss
.section .text
.global _start
_start:
movq $64, mydata
and the results
Code:
example 1 RIP-relative addressing
code1: file format elf64-x86-64
Disassembly of section .text:
00000000004000b0 :
4000b0: 48 c7 87 bc 00 60 00 movq $0x40,0x6000bc(%rdi)
4000b7: 40 00 00 00
Code:
example 2
code2: file format elf64-x86-64
Disassembly of section .text:
00000000004000b0 :
4000b0: 48 c7 04 25 bc 00 60 movq $0x40,0x6000bc
4000b7: 00 40 00 00 00
are we talking about a one byte reduction in code size every time I use RIP relative addressing?
[/text]
Typical RIP and EIP Knowledge
[text]
How RIP/EIP relative addressing works in 32-bit mode
In 32-bit programs you can’t do this :
mov al, [eip]
But you will have to do something like this instead :
call $ + 5
pop ebx
add ebx, 1 + 1 + 1 + 1 ; POP + ADD + ModRM + imm8
mov al, [ebx] ; EBX is now pointing to this instruction!
How RIP/EIP relative addressing works in 64-bit mode
In 64-bit programs you are allowed to write this :
mov al, [rip]
[/text]
LINK
http://developers.sun.com/solaris/articles/x64_dbx.html
https://en.wikipedia.org/wiki/Processor_register
http://www.codegurus.be/codegurus/Programming/riprelativeaddressing_en.htm
http://www.linuxforums.org/forum/linux-programming-scripting/131795-amd-64-bit-rip-relative-addressing.html
The instruction pointer is called ip in 16-bit mode, eip in 32-bit mode,,
and rip in 64-bit mode. The instruction pointer register points to the
memory address which the processor will next attempt to execute; it
cannot be directly accessed in 16-bit or 32-bit mode, but a sequence
like the following can be written to put the address of next_line into
eax:
call next_line
next_line:
pop eax
source :
http://en.wikipedia.org/wiki/X86_assembly_language
(gdb) info registers rax 0xfffffffffffffdfc -516 rbx 0x5dc 1500 rcx 0xffffffffffffffff -1 rdx 0x5dc 1500 rsi 0x1 1 rdi 0x7fff09cf5780 140733357971328 rbp 0x2051160 0x2051160 rsp 0x7fff09cf5730 0x7fff09cf5730 r8 0x0 0 r9 0xffffffff 4294967295 r10 0x8 8 r11 0x246 582 r12 0x7fff09cf5780 140733357971328 r13 0x7fff09cf5790 140733357971344 r14 0x0 0 r15 0x1 1 rip 0x7f2e947000c8 0x7f2e947000c8 eflags 0x246 [ PF ZF IF ] cs 0x33 51 ss 0x2b 43 ds 0x0 0 es 0x0 0 fs 0x0 0 gs 0x0 0 (gdb)
rip 0x7f2e947000c8 0x7f2e947000c8
The RIP register is the instruction pointer register. In 64-bit mode, the RIP register is extended to 64 bits to support 64-bit offsets. In 32-bit x86 architecture, the instruction pointer register is the EIP register. source: http://developers.sun.com/solaris/articles/x64_dbx.html
Hi...I'm teaching myself some AMD 64 bit assembler programing and I'm curious about RIP relative addressing. The docs that I've read state "You are recommended to use RIP relative addressing whenever possible to reduce code size" now my question is, is this the code size reduction they are talking about Code: example code 1 RIP-relative addressing .section .data mydata: .long 0 .section .bss .section .text .global _start _start: movq $64, mydata(%rdi) Code: example code 2 .section .data mydata: .long 0 .section .bss .section .text .global _start _start: movq $64, mydata and the results Code: example 1 RIP-relative addressing code1: file format elf64-x86-64 Disassembly of section .text: 00000000004000b0 : 4000b0: 48 c7 87 bc 00 60 00 movq $0x40,0x6000bc(%rdi) 4000b7: 40 00 00 00 Code: example 2 code2: file format elf64-x86-64 Disassembly of section .text: 00000000004000b0 : 4000b0: 48 c7 04 25 bc 00 60 movq $0x40,0x6000bc 4000b7: 00 40 00 00 00 are we talking about a one byte reduction in code size every time I use RIP relative addressing? source : http://www.linuxforums.org/forum/linux-programming-scripting/131795-amd-64-bit-rip-relative-addressing.html
How RIP/EIP relative addressing works in 32-bit mode In 32-bit programs you can't do this : mov al, [eip] But you will have to do something like this instead : call $ + 5 pop ebx add ebx, 1 + 1 + 1 + 1 ; POP + ADD + ModRM + imm8 mov al, [ebx] ; EBX is now pointing to this instruction! How RIP/EIP relative addressing works in 64-bit mode In 64-bit programs you are allowed to write this : mov al, [rip] source : http://www.codegurus.be/codegurus/Programming/riprelativeaddressing_en.htm
software | Windows |
The Intel IA32 processors have a base pointer register called EBP . The EBP register is typically set to the value of the ESP register at the beginning of a procedure, and used to address the procedure arguments and locally allocated variables throughout the procedure. Thus, the arguments are located at positive offsets from the EBP register, while the variables are located at negative offsets from the EBP register. source : http://d3s.mff.cuni.cz/~ceres/sch/osy/text/ch03s02s02.php
software | GNU/Linux |
(gdb) info registers rax 0xfffffffffffffdfc -516 rbx 0x5dc 1500 rcx 0xffffffffffffffff -1 rdx 0x5dc 1500 rsi 0x1 1 rdi 0x7ffffb2814d0 140737407096016 rbp 0x1f70160 0x1f70160 rsp 0x7ffffb281480 0x7ffffb281480 r8 0x0 0 r9 0xffffffff 4294967295 r10 0x8 8 r11 0x246 582 r12 0x7ffffb2814d0 140737407096016 r13 0x7ffffb2814e0 140737407096032 r14 0x0 0 r15 0x1 1 rip 0x7f668b3710c8 0x7f668b3710c8 eflags 0x246 [ PF ZF IF ] cs 0x33 51 ss 0x2b 43 ds 0x0 0 es 0x0 0 fs 0x0 0 gs 0x0 0 (gdb)rbp 0x1f70160 0x1f70160
In computer architecture, a processor register (or general purpose register) is a small amount of storage available on the CPU whose contents can be accessed more quickly than storage available elsewhere. source : http://en.wikipedia.org/wiki/Processor_register The AMD64 architecture has sixteen 64-bit general purpose registers (GPRs): RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, R8, R9, R10, R11, R12, R13, R14, and R15. Compared to the x86 architecture, the AMD64 architecture has eight new GPRs. source : http://developers.sun.com/solaris/articles/x64_dbx.html
| Related Discussion |
Hi, Could somebody please explain what GCC is doing for this piece of code? What is it initializing? The original code is:
#include
int main()
{
}
And it was translated to:
.file "test1.c"
.def ___main; .scl 2; .type 32; .endef
.text
.globl _main
.def _main; .scl 2; .type 32; .endef
_main:
pushl %ebp
movl %esp, %ebp
subl $8, %esp
andl $-16, %esp
movl $0, %eax
addl $15, %eax
addl $15, %eax
shrl $4, %eax
sall $4, %eax
movl %eax, -4(%ebp)
movl -4(%ebp), %eax
call __alloca
call ___main
leave
ret
| Variation |
Registers E(SP), E(IP) and E(BP) are promoted to 64-bits and are re-named RSP, RIP, and RBP respectively. source and link(s) : http://x86asm.net/articles/x86-64-tour-of-intel-manuals/
software | Windows |
EDI: The Destination Index Every loop that generates data must store the result in memory, and doing so requires a moving pointer. The destination index, EDI, is that pointer. The destination index holds the implied write address of all string operations. The most useful string instruction, remarkably enough, is the seldom-used STOS. STOS copies data from the accumulator into memory and increments the destination index. This one-byte instruction is perfect, since the final result of any calculation should be in the accumulator anyhow, and storing results in a moving memory address is a common task. source : http://www.swansontec.com/sregisters.html
software | GNU/Linux |
(gdb) info registers rax 0xfffffffffffffdfc -516 rbx 0x5dc 1500 rcx 0xffffffffffffffff -1 rdx 0x5dc 1500 rsi 0x1 1 rdi 0x7fffedb60c40 140737181518912 rbp 0x23c7160 0x23c7160 rsp 0x7fffedb60bf0 0x7fffedb60bf0 r8 0x0 0 r9 0xffffffff 4294967295 r10 0x8 8 r11 0x246 582 r12 0x7fffedb60c40 140737181518912 r13 0x7fffedb60c50 140737181518928 r14 0x0 0 r15 0x1 1 rip 0x7fc4a09070c8 0x7fc4a09070c8 eflags 0x246 [ PF ZF IF ] cs 0x33 51 ss 0x2b 43 ds 0x0 0 es 0x0 0 fs 0x0 0 gs 0x0 0 (gdb)rdi 0x7fffedb60c40 140737181518912
The RAX, RBX, RCX, RDX, RBP, RSI, RDI, and RSP registers are used by both 32-bit and 64-bit binaries. However, in 32-bit mode, only the low 32 bits of these registers are accessible by 32-bit binaries. In the x86 architecture, these registers are EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP. source : http://developers.sun.com/solaris/articles/x64_dbx.html
| Related Discussion |
knut st. osmundsen 2007-02-09 18:29:55 EST Description of problem: Crashing at __lll_mutex_timedlock_wait+148 (/lib64/tls/libpthread.so.0): lock cmpxchg %edx,(%rdi) Because the syscall wasn't made and %rdi hasn't been loaded with %r12 yet. Version-Release number of selected component (if applicable): glibc-3.4.0 How to fix: Move the mov %r12,%rdi instruction up somewhere before the je 8f. How to reproduce: This isn't easy to reproduce and I'm not going to write a testcase for it since it's a very obvious bug in the code. But, my from the situation I get it in is that it requires a 2nd thread to signal the condition variable /mutex (I'm not quite sure which it is) while the crashing thread is engaging a sleep. source : https://bugzilla.redhat.com/show_bug.cgi?id=228103
| Variation |
Hardware 64 bit. Windows OS 32 bit so uses EDI. GNU/Linux 64 bit version so used RDI. Links(s). http://archive.midrange.com/wdsci-l/200903/msg00083.html
These instructions read a full pointer from memory and store it in the selected segment register:register pair. The full pointer loads 16 bits into the segment register SS, DS, ES, FS, or GS source : http://pdos.csail.mit.edu/6.828/2008/readings/i386/LGS.htm
(gdb) info registers rax 0xfffffffffffffdfc -516 rbx 0x5dc 1500 rcx 0xffffffffffffffff -1 rdx 0x5dc 1500 rsi 0x1 1 rdi 0x7fff599ac280 140734696702592 rbp 0x1f08af0 0x1f08af0 rsp 0x7fff599ac230 0x7fff599ac230 r8 0x0 0 r9 0xffffffff 4294967295 r10 0x8 8 r11 0x246 582 r12 0x7fff599ac280 140734696702592 r13 0x7fff599ac290 140734696702608 r14 0x0 0 r15 0x1 1 rip 0x7f0129e710c8 0x7f0129e710c8 eflags 0x246 [ PF ZF IF ] cs 0x33 51 ss 0x2b 43 ds 0x0 0 es 0x0 0 fs 0x0 0 gs 0x0 0 (gdb) Instead of FS segment descriptor on x86 versions of the Windows NT family, GS segment descriptor is used to point to two operating system defined structures: Thread Information Block (NT_TIB) in user mode and Processor Control Region (KPCR) in kernel mode. Thus, for example, in user mode GS:0 is the address of the first member of the Thread Information Block. Maintaining this convention made the x86-64 port easier, but required AMD to retain the function of the FS and GS segments in long mode — even though segmented addressing per se is not really used by any modern operating system.[38] source : http://en.wikipedia.org/wiki/X86-64
leilei wrote: I am writting a program for target board which have a 486 cpu, 512K ram(0x0 to 0x7ffff), 512k flash (0x80000 to 0xFFFFF).My program will be burned into flash. My program is to initialize the GDT, IDT, TSS, move them to memory. Now I can enter protected model and mov GDT, IDT correctly.But when I am about to mov TSS, some exception came out, and the CPU reset automaticly. The code casue the problem is like this: mov cx, gdt_idx mov gs, cx when cpu run to the instuction 'mov gs, cx', CPU will reset. i can assure the value in cx is correctly. can any one give me some tips about how can this be happend? This seems to have nothing to do with TSS, yet. The CPU is not happy with the selector attempted to load GS with. Please check that the number in CX is a valid GDT selector within the table range. It also seems that there is no handler available for the exception generated by the segment loading. -- Tauno Voipio tauno voipio (at) iki fi source : http://coding.derkeiler.com/Archive/General/comp.arch.embedded/2008-04/msg01432.html
| Variation |
I think eax has a typical closer connection to 32 bit software architecture of an operating system and rax is like for 64 bit OS. Link(s). http://lists.xensource.com/archives/html/xen-devel/2006-12/msg00547.html
(gdb) info auxv 33 AT_SYSINFO_EHDR System-supplied DSO's ELF header 0x7fff7a9ff000 16 AT_HWCAP Machine-dependent CPU capability hints 0x78bfbff 6 AT_PAGESZ System page size 4096 17 AT_CLKTCK Frequency of times() 100 3 AT_PHDR Program headers for program 0x400040 4 AT_PHENT Size of program header entry 56 5 AT_PHNUM Number of program headers 8 7 AT_BASE Base address of interpreter 0x7f382489e000 8 AT_FLAGS Flags 0x0 9 AT_ENTRY Entry point of program 0x4028e0 11 AT_UID Real user ID 1000 12 AT_EUID Effective user ID 1000 13 AT_GID Real group ID 1000 14 AT_EGID Effective group ID 1000 23 AT_SECURE Boolean, was exec setuid-like? 0 25 AT_RANDOM Address of 16 random bytes 0x7fff7a9b5839 31 AT_EXECFN File name of executable 0x7fff7a9b7fea "/usr/bin/htop" 15 AT_PLATFORM String identifying platform 0x7fff7a9b5849 "x86_64" 0 AT_NULL End of vector 0x0 (gdb)
Display the inferior's auxiliary vector.
That means acting as a subsidiary and kind of one dimensional array.
typedef struct
{
long int a_type; /* Entry type */
union
{
long int a_val; /* Integer value */
void *a_ptr; /* Pointer value */
void (*a_fcn) (void); /* Function pointer value */
} a_un;
} auxv_t;
48: /proc/PID/auxv, which is a common method for native targets. */
49:
50: extern LONGEST procfs_xfer_auxv (struct target_ops *ops,
src/gdb/auxv.c
30: #include "auxv.h"
31: #include "elf/common.h"
37: /* This function handles access via /proc/PID/auxv, which is a common method
38: for native targets. */
50: pathname = xstrprintf ("/proc/%d/auxv", PIDGET (inferior_ptid));
51: fd = open (pathname, writebuf != NULL ? O_WRONLY : O_RDONLY);
github.com/atgreen/moxiedev.git - GPL - C
Mesa/src/mesa/ppc/common_ppc.c - 56 identical
60: Elf64_auxv_t v;
61: #else
62: Elf32_auxv_t v;
100: sprintf( file_name, "/proc/%u/auxv", (unsigned) my_pid );
66: f = fopen( file_name, "rb" );
www.w3.org/Amaya/Distribution/amaya-lib-src-9.54.tgz - Unknown - C
$sudo hexdump /proc/1045/auxv 0000000 0021 0000 0000 0000 f000 e87f 7fff 0000 0000010 0010 0000 0000 0000 fbff 078b 0000 0000 0000020 0006 0000 0000 0000 1000 0000 0000 0000 0000030 0011 0000 0000 0000 0064 0000 0000 0000 0000040 0003 0000 0000 0000 0040 0040 0000 0000 0000050 0004 0000 0000 0000 0038 0000 0000 0000 0000060 0005 0000 0000 0000 0008 0000 0000 0000 0000070 0007 0000 0000 0000 2000 d5a6 7f94 0000 0000080 0008 0000 0000 0000 0000 0000 0000 0000 0000090 0009 0000 0000 0000 1c60 0040 0000 0000 00000a0 000b 0000 0000 0000 0000 0000 0000 0000 00000b0 000c 0000 0000 0000 0000 0000 0000 0000 00000c0 000d 0000 0000 0000 0000 0000 0000 0000 00000d0 000e 0000 0000 0000 0000 0000 0000 0000 00000e0 0017 0000 0000 0000 0000 0000 0000 0000 00000f0 0019 0000 0000 0000 b1d9 e87a 7fff 0000 0000100 001f 0000 0000 0000 bfe8 e87a 7fff 0000 0000110 000f 0000 0000 0000 b1e9 e87a 7fff 0000 0000120 0000 0000 0000 0000 0000 0000 0000 0000 0000130 $
The auxiliary vector is intended for passing information from the operating system to a program interpreter, such as /lib/ld-lsb-ia64.so.1. source : Linux Standard Base Specification for the Itanium™ Architecture 1.3
(gdb) info auxv 33 AT_SYSINFO_EHDR System-supplied DSO's ELF header 0x7fff7a9ff000 16 AT_HWCAP Machine-dependent CPU capability hints 0x78bfbff 6 AT_PAGESZ System page size 4096 17 AT_CLKTCK Frequency of times() 100 3 AT_PHDR Program headers for program 0x400040 4 AT_PHENT Size of program header entry 56 5 AT_PHNUM Number of program headers 8 7 AT_BASE Base address of interpreter 0x7f382489e000 8 AT_FLAGS Flags 0x0 9 AT_ENTRY Entry point of program 0x4028e0 11 AT_UID Real user ID 1000 12 AT_EUID Effective user ID 1000 13 AT_GID Real group ID 1000 14 AT_EGID Effective group ID 1000 23 AT_SECURE Boolean, was exec setuid-like? 0 25 AT_RANDOM Address of 16 random bytes 0x7fff7a9b5839 31 AT_EXECFN File name of executable 0x7fff7a9b7fea "/usr/bin/htop" 15 AT_PLATFORM String identifying platform 0x7fff7a9b5849 "x86_64" 0 AT_NULL End of vector 0x0 (gdb)
Display the inferior's auxiliary vector.
That means acting as a subsidiary and kind of one dimensional array.
typedef struct
{
long int a_type; /* Entry type */
union
{
long int a_val; /* Integer value */
void *a_ptr; /* Pointer value */
void (*a_fcn) (void); /* Function pointer value */
} a_un;
} auxv_t;
48: /proc/PID/auxv, which is a common method for native targets. */
49:
50: extern LONGEST procfs_xfer_auxv (struct target_ops *ops,
src/gdb/auxv.c
30: #include "auxv.h"
31: #include "elf/common.h"
37: /* This function handles access via /proc/PID/auxv, which is a common method
38: for native targets. */
50: pathname = xstrprintf ("/proc/%d/auxv", PIDGET (inferior_ptid));
51: fd = open (pathname, writebuf != NULL ? O_WRONLY : O_RDONLY);
github.com/atgreen/moxiedev.git - GPL - C
Mesa/src/mesa/ppc/common_ppc.c - 56 identical
60: Elf64_auxv_t v;
61: #else
62: Elf32_auxv_t v;
65: sprintf( file_name, "/proc/%u/auxv", (unsigned) my_pid );
66: f = fopen( file_name, "rb" );
www.w3.org/Amaya/Distribution/amaya-lib-src-9.54.tgz - Unknown - C
$sudo hexdump /proc/1045/auxv 0000000 0021 0000 0000 0000 f000 e87f 7fff 0000 0000010 0010 0000 0000 0000 fbff 078b 0000 0000 0000020 0006 0000 0000 0000 1000 0000 0000 0000 0000030 0011 0000 0000 0000 0064 0000 0000 0000 0000040 0003 0000 0000 0000 0040 0040 0000 0000 0000050 0004 0000 0000 0000 0038 0000 0000 0000 0000060 0005 0000 0000 0000 0008 0000 0000 0000 0000070 0007 0000 0000 0000 2000 d5a6 7f94 0000 0000080 0008 0000 0000 0000 0000 0000 0000 0000 0000090 0009 0000 0000 0000 1c60 0040 0000 0000 00000a0 000b 0000 0000 0000 0000 0000 0000 0000 00000b0 000c 0000 0000 0000 0000 0000 0000 0000 00000c0 000d 0000 0000 0000 0000 0000 0000 0000 00000d0 000e 0000 0000 0000 0000 0000 0000 0000 00000e0 0017 0000 0000 0000 0000 0000 0000 0000 00000f0 0019 0000 0000 0000 b1d9 e87a 7fff 0000 0000100 001f 0000 0000 0000 bfe8 e87a 7fff 0000 0000110 000f 0000 0000 0000 b1e9 e87a 7fff 0000 0000120 0000 0000 0000 0000 0000 0000 0000 0000 0000130 $
The auxiliary vector is intended for passing information from the operating system to a program interpreter, such as /lib/ld-lsb-ia64.so.1. source : Linux Standard Base Specification for the Itanium™ Architecture 1.3